117 search results - page 10 / 24 » NOC architecture design for multi-cluster chips |
CCECE
2006
IEEE
14 years 1 months ago
2006
IEEE
Real Time embedded system designers are facing extreme challenges in underlying architectural design selection. It involves the selection of a programmable, concurrent, heterogene...
DATE
2003
IEEE
14 years 27 days ago
2003
IEEE
Managing the complexity of designing chips containing billions of transistors requires decoupling computation from communication. For the communication, scalable and compositional...
FPL
2009
Springer
14 years 7 days ago
2009
Springer
Networks-on-Chips (NoCs) are an emerging communication topology paradigm in single chip VLSI design, enhancing parallelism and system scalability. Processing units (PUs) connect t...
IESS
2007
Springer
14 years 1 months ago
2007
Springer
NoCs present a possible communication infrastructure solution to deal with increased design complexity and shrinking time-to-market. The communication infrastructure is a signific...
DAC
2006
ACM
14 years 1 months ago
2006
ACM
A novel routing algorithm, namely dynamic XY (DyXY) routing, is proposed for NoCs to provide adaptive routing and ensure deadlock-free and livelock-free routing at the same time. ...