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DATE
2002
IEEE
84views Hardware» more  DATE 2002»
14 years 3 months ago
Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP Applications
Microprocessors are today getting more and more inefficient for a growing range of applications. Its principles -The Von Neumann paradigm[3]- based on the sequential execution of ...
Gilles Sassatelli, Lionel Torres, Pascal Benoit, T...
ESA
1999
Springer
95views Algorithms» more  ESA 1999»
14 years 2 months ago
A Fast General Methodology for Information - Theoretically Optimal Encodings of Graphs
We propose a fast methodology for encoding graphs with information-theoretically minimum numbers of bits. Specifically, a graph with property π is called a π-graph. If π satis...
Xin He, Ming-Yang Kao, Hsueh-I Lu
ICCAD
1994
IEEE
117views Hardware» more  ICCAD 1994»
14 years 2 months ago
Optimization of critical paths in circuits with level-sensitive latches
A simple extension of the critical path method is presented which allows more accurate optimization of circuits with level-sensitive latches. The extended formulation provides a s...
Timothy M. Burks, Karem A. Sakallah
FPGA
2004
ACM
163views FPGA» more  FPGA 2004»
14 years 1 months ago
Time and area efficient pattern matching on FPGAs
Pattern matching for network security and intrusion detection demands exceptionally high performance. Much work has been done in this field, and yet there is still significant roo...
Zachary K. Baker, Viktor K. Prasanna
AAAI
2004
13 years 11 months ago
Combinatorial Auctions with Structured Item Graphs
Combinatorial auctions (CAs) are important mechanisms for allocating interrelated items. Unfortunately, winner determination is NP-complete unless there is special structure. We s...
Vincent Conitzer, Jonathan Derryberry, Tuomas Sand...