230 search results - page 10 / 46 » Network Topologies and Consumption Externalities |
HPCA
2009
IEEE
14 years 8 months ago
2009
IEEE
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
ICONIP
2010
13 years 4 months ago
2010
Abstract. We investigated the network topology organized through spike-timingdependent plasticity (STDP) using pair- and triad-connectivity patterns, considering di erence of excit...
DATE
2008
IEEE
14 years 1 months ago
2008
IEEE
In this paper, we use the generalized binary de Bruijn (GBDB) graph as a scalable and efficient network topology for an on-chip communication network. Using just two-layer wiring,...
IMC
2010
ACM
13 years 5 months ago
2010
ACM
Current large-scale topology mapping systems require multiple days to characterize the Internet due to the large amount of probing traffic they incur. The accuracy of maps from ex...
DATE
2010
IEEE
13 years 6 months ago
2010
IEEE
Abstract—On-chip interconnection network is a crucial design component in high-performance System-on-Chips (SoCs). Many of previous works have focused on the automation of its to...