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» Network-on-Chip Architecture Exploration Framework
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TSE
2002
122views more  TSE 2002»
13 years 7 months ago
Virtual Benchmarking and Model Continuity in Prototyping Embedded Multiprocessor Signal Processing Systems
The complexity of hardware/software codesign of embedded real-time signal processing systems can be reduced by rapid system prototyping (RSP). However, existing RSP frameworks do n...
Randall S. Janka, Linda M. Wills, Lewis B. Baumsta...
SCP
2010
154views more  SCP 2010»
13 years 6 months ago
An algebraic foundation for automatic feature-based program synthesis
Feature-Oriented Software Development provides a multitude of formalisms, methods, languages, and tools for building variable, customizable, and extensible software. Along differe...
Sven Apel, Christian Lengauer, Bernhard Mölle...
IPPS
2010
IEEE
13 years 5 months ago
Distributed advance network reservation with delay guarantees
New architectures have recently been proposed and deployed to support end-to-end advance reservation of network resources. These architectures rely on the use a centralized schedul...
Niloofar Fazlollahi, David Starobinski
FDL
2003
IEEE
14 years 25 days ago
Using Rewriting-Logic Notation for Funcional Verification in Data-Stream Based Reconfigurable Computing
Reconfigurable Systolic Arrays are a generalization of Systolic Arrays where node operations and interconnections can be redefined even at run time. This flexibility increases the...
Mauricio Ayala-Rincón, Ricardo P. Jacobi, C...
ICCAD
1999
IEEE
115views Hardware» more  ICCAD 1999»
13 years 12 months ago
Fast performance analysis of bus-based system-on-chip communication architectures
This paper addresses the problem of efficient and accurate performance analysis to drive the exploration and design of bus-based System-on-Chip (SOC) communication architectures. ...
Kanishka Lahiri, Anand Raghunathan, Sujit Dey