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ANCS
2007
ACM
13 years 11 months ago
Design of adaptive communication channel buffers for low-power area-efficient network-on-chip architecture
Network-on-Chip (NoC) architectures provide a scalable solution to the wire delay constraints in deep submicron VLSI designs. Recent research into the optimization of NoC architec...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri
BMCBI
2004
169views more  BMCBI 2004»
13 years 7 months ago
A power law global error model for the identification of differentially expressed genes in microarray data
Background: High-density oligonucleotide microarray technology enables the discovery of genes that are transcriptionally modulated in different biological samples due to physiolog...
Norman Pavelka, Mattia Pelizzola, Caterina Vizzard...
ICWSM
2009
13 years 5 months ago
Information Cascades in the Blogosphere: A Look Behind the Curtain
With an increasing number of people that read, write and comment on blogs, the blogosphere has established itself as an essential medium of communication. A fundamental characteri...
Manos Papagelis, Nilesh Bansal, Nick Koudas
ICCAD
2003
IEEE
195views Hardware» more  ICCAD 2003»
14 years 20 days ago
Vectorless Analysis of Supply Noise Induced Delay Variation
The impact of power supply integrity on a design has become a critical issue, not only for functional verification, but also for performance verification. Traditional analysis has...
Sanjay Pant, David Blaauw, Vladimir Zolotov, Savit...
IWCMC
2010
ACM
14 years 14 days ago
Energy-aware online routing with QoS constraints in multi-rate wireless ad hoc networks
Wireless ad hoc networks consist of hundreds to thousands of mobile nodes that are powered by batteries. To prolong the network operational time, energy conservation in such netwo...
Wei Yang, Weifa Liang, Jun Luo, Wenhua Dou