208 search results - page 11 / 42 » New Directions in Debugging Hardware Designs |
ICCD
2006
IEEE
14 years 4 months ago
2006
IEEE
— As silicon CMOS devices are scaled down into the nanoscale regime, new challenges at both the device and system level are arising. While some of these challenges will be overco...
ICCAD
1999
IEEE
13 years 11 months ago
1999
IEEE
This paper presents a new method to synthesize timed asynchronous circuits directly from the specification without generating a state graph. The synthesis procedure begins with a ...
FPGA
2010
ACM
13 years 7 months ago
2010
ACM
We use reconfigurable hardware to construct a high throughput Bayesian computing machine (BCM) capable of evaluating probabilistic networks with arbitrary DAG (directed acyclic gr...
ISQED
2011
IEEE
12 years 11 months ago
2011
IEEE
The extent to which the 6T SRAM bit cell can be perpetuated through continued scaling is of enormous technological and economic importance. Understanding the growing limitations i...
VSTTE
2005
Springer
14 years 29 days ago
2005
Springer
The interplay back and forth between software model checking and hardware model checking has been fruitful for both. Originally intended for the analysis of concurrent software, mo...