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» New Directions in Debugging Hardware Designs
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ICIP
2004
IEEE
14 years 9 months ago
New scaling technique for direct mode coding in B pictures
To leave the maximum flexibility in encoder to optimize the trade-off between coding performance and complexity, in video coding standards such as H.264/AVC [1], H.263 [2] and MPE...
Xiangyang Ji, Debin Zhao, Wen Gao, Yan Lu, Siwei M...
CEC
2009
IEEE
13 years 11 months ago
JubiTool: Unified design flow for the Perplexus SIMD hardware accelerator
This paper presents a new unified design flow developed within the Perplexus project that aims to accelerate parallelizable data-intensive applications in the context of ubiquitous...
Olivier Brousse, Jérémie Guillot, Th...
DATE
2003
IEEE
135views Hardware» more  DATE 2003»
14 years 23 days ago
Creating Value Through Test
Test is often seen as a necessary evil; it is a fact of life that ICs have manufacturing defects and those need to be filtered out by testing before the ICs are shipped to the cu...
Erik Jan Marinissen, Bart Vermeulen, Robert Madge,...
ASPDAC
2000
ACM
95views Hardware» more  ASPDAC 2000»
13 years 12 months ago
FSM decomposition by direct circuit manipulation applied to low power design
Abstract— Clock-gating techniques are very effective in the reduction of the switching activity in sequential logic circuits. In particular, recent work has shown that significa...
José C. Monteiro, Arlindo L. Oliveira
ISQED
2006
IEEE
101views Hardware» more  ISQED 2006»
14 years 1 months ago
Compiler-Directed Power Density Reduction in NoC-Based Multi-Core Designs
As transistor counts keep increasing and clock frequencies rise, high power consumption is becoming one of the most important obstacles, preventing further scaling and performance...
Sri Hari Krishna Narayanan, Mahmut T. Kandemir, Oz...