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IPPS
1996
IEEE
13 years 12 months ago
A New Approach to Pipeline FFT Processor
A new VLSI architecture for real-time pipeline FFT processor is proposed. A hardware oriented radix-22 algorithm is derived by integrating a twiddle factor decomposition technique ...
Shousheng He, Mats Torkelson
ICCAD
2006
IEEE
111views Hardware» more  ICCAD 2006»
14 years 4 months ago
Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAs
This work describes a new mapping technique, RAM-MAP, that identifies parts of circuits that can be efficiently mapped into the synchronous embedded memories found on field prog...
Gordon R. Chiu, Deshanand P. Singh, Valavan Manoha...
FPGA
2005
ACM
95views FPGA» more  FPGA 2005»
14 years 1 months ago
The Stratix II logic and routing architecture
This paper describes the Altera Stratix II™ logic and routing architecture. This architecture features a novel adaptive logic module (ALM) that is based on a 6-LUT, but can be p...
David M. Lewis, Elias Ahmed, Gregg Baeckler, Vaugh...
ASAP
2003
IEEE
153views Hardware» more  ASAP 2003»
14 years 29 days ago
Hardware Synthesis for Multi-Dimensional Time
This paper introduces basic principles for extending the classical systolic synthesis methodology to multi-dimensional time. Multi-dimensional scheduling enables complex algorithm...
Anne-Claire Guillou, Patrice Quinton, Tanguy Risse...
TVLSI
2010
13 years 2 months ago
Enhancing the Area Efficiency of FPGAs With Hard Circuits Using Shadow Clusters
There is a dramatic logic density gap between FPGAs and ASICs, and this gap is the main reason FPGAs are not cost-effective in high volume applications. Modern FPGAs narrow this ga...
Peter A. Jamieson, Jonathan Rose