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» New Non-Volatile Memory Structures for FPGA Architectures
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DATE
2007
IEEE
114views Hardware» more  DATE 2007»
14 years 2 months ago
Two-level microprocessor-accelerator partitioning
The integration of microprocessors and field-programmable gate array (FPGA) fabric on a single chip increases both the utility and necessity of tools that automatically move softw...
Scott Sirowy, Yonghui Wu, Stefano Lonardi, Frank V...
ISCA
2010
IEEE
205views Hardware» more  ISCA 2010»
14 years 23 days ago
The virtual write queue: coordinating DRAM and last-level cache policies
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...
FCCM
2007
IEEE
111views VLSI» more  FCCM 2007»
14 years 2 months ago
A Structural Object Programming Model, Architecture, Chip and Tools for Reconfigurable Computing
A new platform for reconfigurable computing has an object-based programming model, with architecture, silicon and tools designed to faithfully realize this model. The platform is ...
Michael Butts, Anthony Mark Jones, Paul Wasson
CORR
2008
Springer
117views Education» more  CORR 2008»
13 years 7 months ago
A High Performance Memory Database for Web Application Caches
This paper presents the architecture and characteristics of a memory database intended to be used as a cache engine for web applications. Primary goals of this database are speed a...
Ivan Voras, Danko Basch, Mario Zagar
DAC
2000
ACM
14 years 8 months ago
Hardware-software co-design of embedded reconfigurable architectures
In this paper we describe a new hardware/software partitioning approach for embedded reconfigurable architectures consisting of a general-purpose processor (CPU), a dynamically re...
Yanbing Li, Tim Callahan, Ervan Darnell, Randolph ...