Sciweavers

144 search results - page 24 / 29
» New Non-Volatile Memory Structures for FPGA Architectures
Sort
View
IEEEINTERACT
2003
IEEE
14 years 28 days ago
Compiler-Directed Resource Management for Active Code Regions
Recent studies on program execution behavior reveal that a large amount of execution time is spent in small frequently executed regions of code. Whereas adaptive cache management ...
Ravikrishnan Sree, Alex Settle, Ian Bratt, Daniel ...
ISLPED
2003
ACM
127views Hardware» more  ISLPED 2003»
14 years 28 days ago
Lightweight set buffer: low power data cache for multimedia application
A new architectural technique to reduce power dissipation in data caches is proposed. In multimedia applications, a major portion of data cache accesses hit in the same cache set ...
Jun Yang 0002, Youtao Zhang
ICCAD
1994
IEEE
116views Hardware» more  ICCAD 1994»
13 years 11 months ago
Design of heterogeneous ICs for mobile and personal communication systems
{ Mobile and personal communication systems form key market areas for the electronics industry of the nineties. Stringent requirements in terms of exibility, performance and power...
Gert Goossens, Ivo Bolsens, Bill Lin, Francky Catt...
DAC
2008
ACM
14 years 8 months ago
Miss reduction in embedded processors through dynamic, power-friendly cache design
Today, embedded processors are expected to be able to run complex, algorithm-heavy applications that were originally designed and coded for general-purpose processors. As a result...
Garo Bournoutian, Alex Orailoglu
ACMMSP
2004
ACM
125views Hardware» more  ACMMSP 2004»
14 years 1 months ago
Improving trace cache hit rates using the sliding window fill mechanism and fill select table
As superscalar processors become increasingly wide, it is inevitable that the large set of instructions to be fetched every cycle will span multiple noncontiguous basic blocks. Th...
Muhammad Shaaban, Edward Mulrane