73 search results - page 5 / 15 » New Results on Instruction Cache Attacks |
ISCA
2002
IEEE
14 years 9 days ago
2002
IEEE
This paper investigates a class of main memory accesses (invalid memory traffic) that can be eliminated altogether. Invalid memory traffic is real data traffic that transfers inva...
HIPC
1999
Springer
13 years 11 months ago
1999
Springer
We describe a radically new cache architecture and demonstrate that it offers a huge reduction in cache cost, size and power consumption whilst maintaining performance on a wide ra...
MICRO
2003
IEEE
14 years 20 days ago
2003
IEEE
Wire delays are a major concern for current and forthcoming processors. One approach to attack this problem is to divide the processor into semi-independent units referred to as c...
MICRO
2000
IEEE
13 years 7 months ago
2000
IEEE
This paper demonstrates how an Instruction Path Coprocessor (I-COP) can be efficiently implemented using the PipeRench reconfigurable architecture. An I-COP is a programmable on-c...
MICRO
2003
IEEE
14 years 20 days ago
2003
IEEE
A dynamic optimizer is a runtime software system that groups a program’s instruction sequences into traces, optimizes those traces, stores the optimized traces in a softwarebase...