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DAC
2001
ACM
14 years 9 months ago
LOTTERYBUS: A New High-Performance Communication Architecture for System-on-Chip Designs
This paper presents LOTTERYBUS, a novel high-performance communication architecture for system-on-chip (SoC) designs. The LOTTERYBUS architecture was designed to address the follo...
Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshmi...
TIP
2002
114views more  TIP 2002»
13 years 8 months ago
New architecture for dynamic frame-skipping transcoder
Abstract--Transcoding is a key technique for reducing the bitrate of a previously compressed video signal. A high transcoding ratio may result in an unacceptable picture quality wh...
Kai-Tat Fung, Yui-Lam Chan, Wan-Chi Siu
ARITH
2007
IEEE
14 years 2 months ago
A New Architecture For Multiple-Precision Floating-Point Multiply-Add Fused Unit Design
The floating-point multiply-add fused (MAF) unit sets a new trend in the processor design to speed up floatingpoint performance in scientific and multimedia applications. This ...
Libo Huang, Li Shen, Kui Dai, Zhiying Wang
AISS
2010
118views more  AISS 2010»
13 years 6 months ago
A New Method for Service Binding in Service Oriented Architecture Using Auction Algorithm
One of the important debates in service-oriented architecture is the competitive conditions in the side of service provider and service consumer. In service-oriented architecture ...
Sahar Sohangir, Mir Ali Seyyedi
MICRO
2007
IEEE
120views Hardware» more  MICRO 2007»
14 years 2 months ago
Scavenger: A New Last Level Cache Architecture with Global Block Priority
Addresses suffering from cache misses typically exhibit repetitive patterns due to the temporal locality inherent in the access stream. However, we observe that the number of inte...
Arkaprava Basu, Nevin Kirman, Meyrem Kirman, Maina...