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DAC
2005
ACM
13 years 9 months ago
Multiplexer restructuring for FPGA implementation cost reduction
This paper presents a novel synthesis algorithm that reduces the area needed for implementing multiplexers on an FPGA by an average of 18%. This is achieved by reducing the number...
Paul Metzgen, Dominic Nancekievill
RTSS
1998
IEEE
13 years 11 months ago
Efficient Object Sharing in Quantum-Based Real-Time Systems
We consider the problem of implementing shared objects in uniprocessor and multiprocessor real-time systems in which tasks are executed using a scheduling quantum. In most quantum...
James H. Anderson, Rohit Jain, Kevin Jeffay
SOSP
1997
ACM
13 years 8 months ago
Towards Transparent and Efficient Software Distributed Shared Memory
Despite a large research effort, software distributed shared memory systems have not been widely used to run parallel applications across clusters of computers. The higher perform...
Daniel J. Scales, Kourosh Gharachorloo
DATE
2006
IEEE
82views Hardware» more  DATE 2006»
14 years 1 months ago
Concurrent core test for SOC using shared test set and scan chain disable
A concurrent core test approach is proposed to reduce the test cost of SOC. Multiple cores in SOC can be tested simultaneously by using a shared test set and scan chain disable. P...
Gang Zeng, Hideo Ito
DATE
1999
IEEE
147views Hardware» more  DATE 1999»
13 years 11 months ago
Efficient BIST Hardware Insertion with Low Test Application Time for Synthesized Data Paths
In this paper, new and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis. The methodology is ba...
Nicola Nicolici, Bashir M. Al-Hashimi