152 search results - page 6 / 31 » Noise considerations in circuit optimization |
DAC
1997
ACM
13 years 12 months ago
1997
ACM
This paper describes a new design methodology to analyze the on-chip power supply noise for high performance microprocessors. Based on an integrated package-level and chip-level p...
ICCAD
2008
IEEE
14 years 2 months ago
2008
IEEE
— Dynamic power noises may not only degrade the circuit performance but also reduce the noise margin which may result in the functional errors in integrated circuit. Decoupling c...
DAC
1998
ACM
13 years 11 months ago
1998
ACM
Interconnect-driven optimization is an increasingly important step in high-performance design. Algorithms for buffer insertion have been successfully utilized to reduce delay in gl...
ISPD
2000
ACM
14 years 4 days ago
2000
ACM
We propose a gate resizing method for delay and power optimization that is based on statistical static timing analysis. Our method focuses on the component of timing uncertainties...
ASPDAC
2005
ACM
14 years 1 months ago
2005
ACM
: In ultra-deep submicron VLSI circuits, clock network is a major source of power consumption and power supply noise. Therefore, it is very important to minimize clock network size...