339 search results - page 11 / 68 » Noise-tolerant dynamic circuit design |
ASPDAC
2008
ACM
13 years 10 months ago
2008
ACM
Traditionally, clock network layout is performed after cell placement. Such methodology is facing a serious problem in nanometer IC designs where people tend to use huge clock buff...
ISCAS
2003
IEEE
14 years 1 months ago
2003
IEEE
A closed form expression for the rise time of a gate driving a distributed RLC line is introduced that is within 8% of dynamic circuit simulations for a wide range of RLC loads. I...
DAC
2005
ACM
14 years 9 months ago
2005
ACM
As Si CMOS devices are scaled down into the nanoscale regime, current computer architecture approaches are reaching their practical limits. Future nano-architectures will confront...
NIPS
2000
13 years 9 months ago
2000
Experimental data show that biological synapses behave quite differently from the symbolic synapses in common artificial neural network models. Biological synapses are dynamic, i....
ICCAD
2004
IEEE
14 years 5 months ago
2004
IEEE
Thermal effects are becoming a limiting factor in highperformance circuit design due to the strong temperaturedependence of leakage power, circuit performance, IC package cost and...