339 search results - page 45 / 68 » Noise-tolerant dynamic circuit design |
CCECE
2009
IEEE
14 years 4 months ago
2009
IEEE
A workstation requires a low-power design similar to a typical PC. In this paper we propose several strategies to reduce the power consumption of a workstation. First, we must com...
JCSC
2002
13 years 9 months ago
2002
There is a growing need to analyze and optimize the stand-by component of power in digital circuits designed for portable and battery-powered applications. Since these circuits re...
VLSID
2006
IEEE
14 years 10 months ago
2006
IEEE
This article describes a standard cell based novel implementation of a low-power Viterbi Decoder (VD) targeted for the IEEE 802.11a Wireless LAN system. Multiple clock rates have ...
ISCAS
1999
IEEE
14 years 2 months ago
1999
IEEE
This paper describes a high performance CMOS differential input front-end, designed for optical wireless communications. The front-end achieves a 50 MHz bandwidth and a 400 K tran...
CODES
2007
IEEE
14 years 4 months ago
2007
IEEE
We present a dynamic optimization technique, thread warping, that uses a single processor on a multiprocessor system to dynamically synthesize threads into custom accelerator circ...