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PDP
2011
IEEE
13 years 7 days ago
Quantifying Thread Vulnerability for Multicore Architectures
Abstract—Continuously reducing transistor sizes and aggressive low power operating modes employed by modern architectures tend to increase transient error rates. Concurrently, mu...
Isil Oz, Haluk Rahmi Topcuoglu, Mahmut T. Kandemir...
LCTRTS
2010
Springer
14 years 1 months ago
Cache vulnerability equations for protecting data in embedded processor caches from soft errors
Continuous technology scaling has brought us to a point, where transistors have become extremely susceptible to cosmic radiation strikes, or soft errors. Inside the processor, cac...
Aviral Shrivastava, Jongeun Lee, Reiley Jeyapaul
DAC
2003
ACM
14 years 9 months ago
A survey of techniques for energy efficient on-chip communication
Interconnects have been shown to be a dominant source of energy consumption in modern day System-on-Chip (SoC) designs. With a large (and growing) number of electronic systems bei...
Vijay Raghunathan, Mani B. Srivastava, Rajesh K. G...
DATE
2008
IEEE
223views Hardware» more  DATE 2008»
14 years 3 months ago
Cooperative Safety: a Combination of Multiple Technologies
—Governmental Transportation Authorities' interest in Car to Car and Car to Infrastructure has grown dramatically over the last few years in order to increase the road safet...
Raffaele Penazzi, Piergiorgio Capozio, Martin Dunc...
PPAM
2005
Springer
14 years 2 months ago
A Web Computing Environment for Parallel Algorithms in Java
We present a web computing library (PUBWCL) in Java that allows to execute tightly coupled, massively parallel algorithms in the bulk-synchronous (BSP) style on PCs distributed ove...
Olaf Bonorden, Joachim Gehweiler, Friedhelm Meyer ...