325 search results - page 23 / 65 » Non-uniform Instruction Scheduling |
ASAP
2000
IEEE
13 years 11 months ago
2000
IEEE
Exploiting instruction-level parallelism (ILP) is extremely important for achieving high performance in application specific instruction set processors (ASIPs) and embedded proces...
VLSID
2002
IEEE
14 years 7 months ago
2002
IEEE
This paper shows that software pipelining can be an effective technique for code generation for coarse-grained reconfigurable instruction set processors. The paper describes a tec...
DATE
2008
IEEE
14 years 1 months ago
2008
IEEE
One of the upcoming challenges in embedded processing is to incorporate an increasing amount of adaptivity in order to respond to the multifarious constraints induced by today’s...
DATE
2002
IEEE
14 years 11 days ago
2002
IEEE
The design of application (-domain) specific instructionset processors (ASIPs), optimized for code size, has traditionally been accompanied by the necessity to program assembly, ...
ISCA
1992
IEEE
13 years 11 months ago
1992
IEEE
In this paper, we propose a multithreaded processor architecture which improves machine throughput. In our processor architecture, instructions from different threads (not a singl...