Sciweavers

325 search results - page 6 / 65
» Non-uniform Instruction Scheduling
Sort
View
CASES
2007
ACM
13 years 11 months ago
A backtracking instruction scheduler using predicate-based code hoisting to fill delay slots
Delayed branching is a technique to alleviate branch hazards without expensive hardware branch prediction mechanisms. For VLIW processors with deep pipelines and many issue slots,...
Tom Vander Aa, Bingfeng Mei, Bjorn De Sutter
HEURISTICS
2008
92views more  HEURISTICS 2008»
13 years 7 months ago
Learning heuristics for basic block instruction scheduling
Instruction scheduling is an important step for improving the performance of object code produced by a compiler. A fundamental problem that arises in instruction scheduling is to ...
Abid M. Malik, Tyrel Russell, Michael Chase, Peter...
ICS
1999
Tsinghua U.
13 years 11 months ago
Reorganizing global schedules for register allocation
Instruction scheduling is an important compiler technique for exploiting more instruction-level parallelism (ILP) in high-performance microprocessors, and in this paper, we study ...
Gang Chen, Michael D. Smith
RSP
2000
IEEE
111views Control Systems» more  RSP 2000»
13 years 11 months ago
Reconfigurable Instruction Set Processors: A Survey
Reconfigurable instruction set processors have the capability to adapt their instruction sets to the application being executed through a reconfiguration in their hardware. Throug...
Francisco Barat, Rudy Lauwereins
ISLPED
2005
ACM
150views Hardware» more  ISLPED 2005»
14 years 28 days ago
Instruction packing: reducing power and delay of the dynamic scheduling logic
The instruction scheduling logic used in modern superscalar microprocessors often relies on associative searching of the issue queue entries to dynamically wakeup instructions for...
Joseph J. Sharkey, Dmitry V. Ponomarev, Kanad Ghos...