129 search results - page 21 / 26 » Novel Design Methodology for High-Performance XOR-XNOR Circu... |
GLVLSI
2003
IEEE
14 years 3 months ago
2003
IEEE
The current trends in high performance integrated circuits are towards faster and more powerful circuits in the giga-hertz range and even further. As the more complex Integrated C...
VLSID
2007
IEEE
14 years 10 months ago
2007
IEEE
In the past, Field Programmable Gate Array (FPGA) circuits only contained a limited amount of logic and operated at a low frequency. Few applications running on FPGAs consumed exc...
DAC
2005
ACM
14 years 10 months ago
2005
ACM
The race conditions often limit the smallest feasible clock period that the optimal clock skew scheduling can achieve. Therefore, the combination of clock skew scheduling and dela...
DAC
1996
ACM
14 years 1 months ago
1996
ACM
1- A methodology is presented in this paper for determining an optimal set of clock path delays for designing high performance VLSI/ULSI-based clock distribution networks. This met...
ICCAD
2009
IEEE
13 years 7 months ago
2009
IEEE
Boolean satisfiability (SAT) based methods have traditionally been popular for formally verifying properties for digital circuits. We present a novel methodology for formulating a...