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» Novel Test Pattern Generators for Pseudo-Exhaustive Testing
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DDECS
2007
IEEE
90views Hardware» more  DDECS 2007»
14 years 1 months ago
Test Pattern Generator for Delay Faults
A method of generating test pairs for the delay faults is presented in this paper. The modification of the MISR register gives the source of test pairs. The modification of this r...
Tomasz Rudnicki, Andrzej Hlawiczka
VLSID
2009
IEEE
150views VLSI» more  VLSID 2009»
14 years 9 months ago
TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis
We present the automatic test pattern generator TIGUAN based on a thread-parallel SAT solver. Due to a tight integration of the SAT engine into the ATPG algorithm and a carefully ...
Alejandro Czutro, Ilia Polian, Matthew D. T. Lewis...
ICCD
2004
IEEE
134views Hardware» more  ICCD 2004»
14 years 6 months ago
An Automatic Test Pattern Generation Framework for Combinational Threshold Logic Networks
— We propose an automatic test pattern generation (ATPG) framework for combinational threshold networks. The motivation behind this work lies in the fact that many emerging nanot...
Pallav Gupta, Rui Zhang, Niraj K. Jha
ISOLA
2010
Springer
13 years 7 months ago
Enforcing Applicability of Real-Time Scheduling Theory Feasibility Tests with the Use of Design-Patterns
Abstract. This article deals with performance verifications of architecture models of real-time embedded systems. We focus on models verified with the real-time scheduling theory...
Alain Plantec, Frank Singhoff, Pierre Dissaux, J&e...
EURODAC
1994
IEEE
130views VHDL» more  EURODAC 1994»
14 years 1 months ago
RESIST: a recursive test pattern generation algorithm for path delay faults
This paper presents Resist, a recursive test pattern generation (TPG) algorithm for path delay fault testing of scan-based circuits. In contrast to other approaches, it exploits t...
Karl Fuchs, Michael Pabst, Torsten Rössel