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» Novel Test Pattern Generators for Pseudo-Exhaustive Testing
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ITC
1998
IEEE
120views Hardware» more  ITC 1998»
14 years 1 months ago
Test generation in VLSI circuits for crosstalk noise
This paper addresses the problem of efficiently and accurately generating two-vector tests for crosstalk induced effects, such as pulses, signal speedup and slowdown, in digital c...
Weiyu Chen, Sandeep K. Gupta, Melvin A. Breuer
ITC
1995
IEEE
104views Hardware» more  ITC 1995»
14 years 20 days ago
Synthesis of Mapping Logic for Generating Transformed Pseudo-Random Patterns for BIST
During built-in self-test (BIST), the set of patterns generated by a pseudo-random pattern generator may not provide a sufficiently high fault coverage. This paper presents a new ...
Nur A. Touba, Edward J. McCluskey
DATE
2008
IEEE
109views Hardware» more  DATE 2008»
14 years 3 months ago
Layout-Aware, IR-Drop Tolerant Transition Fault Pattern Generation
— Market and customer demands have continued to push the limits of CMOS performance. At-speed test has become a common method to ensure these high performance chips are being shi...
Jeremy Lee, Sumit Narayan, Mike Kapralos, Mohammad...
ICCAD
2003
IEEE
135views Hardware» more  ICCAD 2003»
14 years 2 months ago
ATPG for Noise-Induced Switch Failures in Domino Logic
Domino circuits have been used in most modern high-performance microprocessor designs because of their high speed, low transistor-count and hazard-free operation. However, with te...
Rahul Kundu, R. D. (Shawn) Blanton
DBPL
2005
Springer
135views Database» more  DBPL 2005»
14 years 2 months ago
Type-Based Optimization for Regular Patterns
Pattern matching mechanisms based on regular expressions feature in a number of recent languages for processing XML. The flexibility of these mechanisms demands novel approaches ...
Michael Y. Levin, Benjamin C. Pierce