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» Novel Test Pattern Generators for Pseudo-Exhaustive Testing
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VTS
1995
IEEE
100views Hardware» more  VTS 1995»
14 years 19 days ago
Transformed pseudo-random patterns for BIST
This paper presents a new approach for on-chip test pattern generation. The set of test patterns generated by a pseudo-random pattern generator (e.g., an LFSR) is transformed into...
Nur A. Touba, Edward J. McCluskey
IEE
2010
185views more  IEE 2010»
13 years 7 months ago
Judy - a mutation testing tool for Java
Popular code coverage measures, such as branch coverage, are indicators of the thoroughness rather than the fault detection capability of test suites. Mutation testing is a fault-...
Lech Madeyski, N. Radyk
ICCAD
2010
IEEE
133views Hardware» more  ICCAD 2010»
13 years 6 months ago
Testing methods for detecting stuck-open power switches in coarse-grain MTCMOS designs
Coarse-grain multi-threshold CMOS (MTCMOS) is an effective power-gating technique to reduce IC's leakage power consumption by turning off idle devices with MTCMOS power switc...
Szu-Pang Mu, Yi-Ming Wang, Hao-Yu Yang, Mango Chia...
DATE
2003
IEEE
90views Hardware» more  DATE 2003»
14 years 2 months ago
Extending JTAG for Testing Signal Integrity in SoCs
As the technology is shrinking and the working frequency is going into multi gigahertz range, the issues related to interconnect testing are becoming more dominant. Specifically,...
Nisar Ahmed, Mohammad H. Tehranipour, Mehrdad Nour...
DFT
2004
IEEE
95views VLSI» more  DFT 2004»
14 years 25 days ago
Mixed Loopback BiST for RF Digital Transceivers
In this paper we analyze the performance of a mixed built-in-self-test (BiST) for RF IC digital transceivers, where a baseband processor can be used both as a test pattern generat...
Jerzy Dabrowski, Javier Gonzalez Bayon