980 search results - page 51 / 196 » Novel Test Pattern Generators for Pseudo-Exhaustive Testing |
ITC
1998
IEEE
14 years 1 months ago
1998
IEEE
This paper presents a logic synthesis tool called BETSY (BIST Environment Testable Synthesis) for synthesizing circuits that achieve complete (100%)fault coverage in a user specif...
COLING
2010
13 years 4 months ago
2010
A new approach has been developed for acquiring bilingual web pages from the result pages of search engines, which is composed of two challenging tasks. The first task is to detec...
TCAD
1998
13 years 8 months ago
1998
—We study the effect of the controller on the testability of sequential circuits composed of controllers and data paths. We show that even when all the loops of the circuit have ...
ISVC
2007
Springer
14 years 3 months ago
2007
Springer
This paper presents a technique that allows test engineers to visually analyze and explore within memory chip test data. We represent the test results from a generation of chips al...
ETS
2006
IEEE
14 years 3 months ago
2006
IEEE
BIST is an attractive approach to detect delay faults due to its inherent support for at-speed test. Deterministic logic BIST (DLBIST) is a technique which was successfully applie...