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» Novel Test Pattern Generators for Pseudo-Exhaustive Testing
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DSD
2006
IEEE
93views Hardware» more  DSD 2006»
14 years 3 months ago
High-Level Decision Diagram based Fault Models for Targeting FSMs
Recently, a number of works have been published on implementing assignment decision diagram models combined with SAT methods to address register-transfer level test pattern genera...
Jaan Raik, Raimund Ubar, Taavi Viilukas
VLSID
2001
IEEE
164views VLSI» more  VLSID 2001»
14 years 9 months ago
An Efficient Parallel Transparent Bist Method For Multiple Embedded Memory Buffers
In this paper, we propose a new transparent built-in self-test ( TBIST ) method to test multiple embedded memory arrays with various sizes in parallel. First, a new transparent tes...
Der-Cheng Huang, Wen-Ben Jone, Sunil R. Das
ISCAS
2007
IEEE
128views Hardware» more  ISCAS 2007»
14 years 3 months ago
SAT-based ATPG for Path Delay Faults in Sequential Circuits
Due to the development of high speed circuits beyond the 2-GHz mark, the significance of automatic test pattern generation for Path Delay Faults (PDFs) drastically increased in t...
Stephan Eggersglüß, Görschwin Fey,...
GCB
2009
Springer
141views Biometrics» more  GCB 2009»
14 years 3 months ago
Discovering Temporal Patterns of Differential Gene Expression in Microarray Time Series
: A wealth of time series of microarray measurements have become available over recent years. Several two-sample tests for detecting differential gene expression in these time seri...
Oliver Stegle, Katherine J. Denby, David L. Wild, ...
ICIP
2009
IEEE
14 years 3 months ago
A Novel Framework for Imaging Using Compressed Sensing
Recently, there has been growing interest in using compressed sensing to perform imaging. Most of these algorithms capture the image of a scene by taking projections of the imaged ...
Pradeep Sen and Soheil Darabi