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GLVLSI
1996
IEEE
125views VLSI» more  GLVLSI 1996»
15 years 10 months ago
Performance-Driven Interconnect Global Routing
In this paper, we propose a global routing algorithm for multi-layer building-block layouts. The algorithm is based on successive ripup and rerouting while satisfying edge capacit...
Dongsheng Wang, Ernest S. Kuh
ICCAD
1994
IEEE
61views Hardware» more  ICCAD 1994»
15 years 10 months ago
Simultaneous driver and wire sizing for performance and power optimization
In this paper, we study the simultaneousdriver and wire sizing (SDWS) problem under two objective functions: (i) delay minimization only, or (ii) combined delay and power dissipat...
Jason Cong, Cheng-Kok Koh
ACSC
2004
IEEE
15 years 9 months ago
Exploiting FPGA Concurrency to Enhance JVM Performance
The Java Programming Language has been praised for its platform independence and portability, but because of its slow execution speed on a software Java Virtual Machine (JVM), som...
James Parnis, Gareth Lee
AICT
2006
IEEE
135views Communications» more  AICT 2006»
15 years 9 months ago
Improving Web Performance through New Networking Technologies
New connection-oriented networking technologies can provide quality-of-service guaranteed network connectivity required by some web-based applications. In this paper, we present a...
Xiuduan Fang, Xuan Zheng, Malathi Veeraraghavan
DSD
2004
IEEE
104views Hardware» more  DSD 2004»
15 years 9 months ago
A Static Low-Power, High-Performance 32-bit Carry Skip Adder
In this paper, we present a full-static carry-skip adder designed to achieve low power dissipation and high-performance operation. To reduce the adder's delay and power consu...
Kai Chirca, Michael J. Schulte, John Glossner, Hao...