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SPAA
2006
ACM
14 years 1 months ago
Modeling instruction placement on a spatial architecture
In response to current technology scaling trends, architects are developing a new style of processor, known as spatial computers. A spatial computer is composed of hundreds or eve...
Martha Mercaldi, Steven Swanson, Andrew Petersen, ...
DAC
2004
ACM
13 years 11 months ago
An SoC design methodology using FPGAs and embedded microprocessors
In System on Chip (SoC) design, growing design complexity has esigners to start designs at higher abstraction levels. This paper proposes an SoC design methodology that makes full...
Nobuyuki Ohba, Kohji Takano
ISCA
2000
IEEE
156views Hardware» more  ISCA 2000»
14 years 3 hour ago
CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit
Reconfigurable hardware has the potential for significant performance improvements by providing support for applicationāˆ’specific operations. We report our experience with Chimae...
Zhi Alex Ye, Andreas Moshovos, Scott Hauck, Prithv...
ICSOC
2007
Springer
14 years 1 months ago
Architectural Decisions and Patterns for Transactional Workflows in SOA
Abstract. An important architectural style for constructing enterprise applications is to use transactional workflows in SOA. In this setting, workflow activities invoke distribute...
Olaf Zimmermann, Jonas Grundler, Stefan Tai, Frank...
ICCAD
2001
IEEE
86views Hardware» more  ICCAD 2001»
14 years 4 months ago
System-Level Exploration for Pareto-Optimal Configurations in Parameterized Systems-on-a-Chip
In this work, we provide a technique for efficiently exploring the configuration space of a parameterized system-on-a-chip (SOC) architecture to find all Pareto-optimal configurat...
Tony Givargis, Frank Vahid, Jörg Henkel