287 search results - page 57 / 58 » On Exploiting Task Duplication in Parallel Program Schedulin... |
BMCBI
2005
13 years 7 months ago
2005
Background: We observe two trends in bioinformatics: (i) analyses are increasing in complexity, often requiring several applications to be run as a workflow; and (ii) multiple CPU...
DAC
2008
ACM
13 years 9 months ago
2008
ACM
The problem attacked in this paper is one of automatically mapping an application onto a Network-on-Chip (NoC) based chip multiprocessor (CMP) architecture in a locality-aware fas...
MICRO
2010
IEEE
13 years 5 months ago
2010
IEEE
SARC merges cache controller and network interface functions by relying on a single hardware primitive: each access checks the tag and the state of the addressed line for possible...
ISCA
1996
IEEE
13 years 11 months ago
1996
IEEE
Many studies have investigated performance improvement through exploiting instruction-level parallelism (ILP) with a particular architecture. Unfortunately, these studies indicate...
MICRO
2000
IEEE
13 years 7 months ago
2000
IEEE
level of abstraction, compared with the program representation for scalar optimizations. For example, loop unrolling and loop unrolland-jam transformations exploit the large regist...