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» On Fault Testing for Reversible Circuits
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ATS
2005
IEEE
132views Hardware» more  ATS 2005»
14 years 2 months ago
Concurrent Test Generation
We define a new type of test, called “concurrent test,” for a combinational circuit. Given a set of target faults, a concurrent-test is an input vector that detects all (or m...
Vishwani D. Agrawal, Alok S. Doshi
GLVLSI
2010
IEEE
209views VLSI» more  GLVLSI 2010»
14 years 1 months ago
Enhancing debugging of multiple missing control errors in reversible logic
Researchers are looking for alternatives to overcome the upcoming limits of conventional hardware technologies. Reversible logic thereby established itself as a promising directio...
Jean Christoph Jung, Stefan Frehse, Robert Wille, ...
COCOON
2010
Springer
14 years 1 months ago
Universal Test Sets for Reversible Circuits
Satoshi Tayu, Shota Fukuyama, Shuichi Ueno
DATE
2009
IEEE
77views Hardware» more  DATE 2009»
14 years 3 months ago
On the relationship between stuck-at fault coverage and transition fault coverage
The single stuck-at fault coverage is often seen as a figure-of-merit also for scan testing according to other fault models like transition faults, bridging faults, crosstalk faul...
Jan Schat
HASE
2007
IEEE
14 years 2 months ago
Advances in Quantum Computing Fault Tolerance and Testing
We study recent developments in quantum computing (QC) testing and fault tolerance (FT) techniques and discuss several attempts to formalize quantum logic fault models. We illustr...
David Y. Feinstein, V. S. S. Nair, Mitchell A. Tho...