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ICCAD
1999
IEEE
86views Hardware» more  ICCAD 1999»
14 years 26 days ago
A framework for testing core-based systems-on-a-chip
Available techniques for testing core-based systems-on-a-chip (SOCs) do not provide a systematic means for synthesising low-overhead test architectures and compact test solutions....
Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jh...
ITC
1997
IEEE
73views Hardware» more  ITC 1997»
14 years 23 days ago
A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems
In a fundamental paradigm shift in system design, entire systems are being built on a single chip, using multiple embedded cores. Though the newest system design methodology has s...
Indradeep Ghosh, Niraj K. Jha, Sujit Dey
SP
2010
IEEE
158views Security Privacy» more  SP 2010»
14 years 13 days ago
Tamper Evident Microprocessors
Abstract—Most security mechanisms proposed to date unquestioningly place trust in microprocessor hardware. This trust, however, is misplaced and dangerous because microprocessors...
Adam Waksman, Simha Sethumadhavan
CIKM
2006
Springer
14 years 9 days ago
KDDCS: a load-balanced in-network data-centric storage scheme for sensor networks
We propose an In-Network Data-Centric Storage (INDCS) scheme for answering ad-hoc queries in sensor networks. Previously proposed In-Network Storage (INS) schemes suffered from St...
Mohamed Aly, Kirk Pruhs, Panos K. Chrysanthis
EDCC
2006
Springer
14 years 7 days ago
SEU Mitigation Techniques for Microprocessor Control Logic
The importance of fault tolerance at the processor architecture level has been made increasingly important due to rapid advancements in the design and usage of high performance de...
T. S. Ganesh, Viswanathan Subramanian, Arun K. Som...