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» On Optimal Tolerancing in Computer-Aided Design
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ICCAD
2003
IEEE
109views Hardware» more  ICCAD 2003»
14 years 4 months ago
Large-Scale Circuit Placement: Gap and Promise
Placement is one of the most important steps in the RTLto-GDSII synthesis process, as it directly defines the interconnects, which have become the bottleneck in circuit and syste...
Jason Cong, Tim Kong, Joseph R. Shinnerl, Min Xie,...
DAC
2006
ACM
14 years 8 months ago
Design automation for DNA self-assembled nanostructures
DNA self-assembly is an emerging technology with potential as a future replacement of conventional lithographic fabrication. A key challenge is the specification of appropriate DN...
Constantin Pistol, Alvin R. Lebeck, Chris Dwyer
ISLPED
2004
ACM
88views Hardware» more  ISLPED 2004»
14 years 28 days ago
Architecting voltage islands in core-based system-on-a-chip designs
Voltage islands enable core-level power optimization for Systemon-Chip (SoC) designs by utilizing a unique supply voltage for each core. Architecting voltage islands involves isla...
Jingcao Hu, Youngsoo Shin, Nagu R. Dhanwada, Radu ...
VLSI
2010
Springer
13 years 5 months ago
Design of low-complexity and high-speed digital Finite Impulse Response filters
—In this paper, we introduce a design methodology to implement low-complexity and high-speed digital Finite Impulse Response (FIR) filters. Since FIR filters suffer from a larg...
Diego Jaccottet, Eduardo Costa, Levent Aksoy, Paul...
SLIP
2006
ACM
14 years 1 months ago
Generation of design guarantees for interconnect matching
Manufacturable design requires matching of interconnects which have equal nominal dimensions. New design rules are projected to bring guarantee rules for interconnect matching. In...
Andrew B. Kahng, Rasit Onur Topaloglu