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» On Reconfigurable Co-processing Units
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CDC
2010
IEEE
181views Control Systems» more  CDC 2010»
13 years 2 months ago
Relationship between power loss and network topology in power systems
This paper is concerned with studying how the minimum power loss in a power system is related to its network topology. The existing algorithms in the literature all exploit nonline...
Javad Lavaei, Steven H. Low
RSP
2000
IEEE
156views Control Systems» more  RSP 2000»
14 years 4 days ago
Quasi-Static Scheduling of Reconfigurable Dataflow Graphs for DSP Systems
Dataflow programming has proven to be popular for representing applications in rapid prototyping tools for digital signal processing (DSP); however, existing dataflow design tools...
Bishnupriya Bhattacharya, Shuvra S. Bhattacharyya
ARC
2007
Springer
150views Hardware» more  ARC 2007»
13 years 11 months ago
MT-ADRES: Multithreading on Coarse-Grained Reconfigurable Architecture
The coarse-grained reconfigurable architecture ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) and its compiler offer high instruction-level parallelism (ILP)...
Kehuai Wu, Andreas Kanstein, Jan Madsen, Mladen Be...
ICCD
2006
IEEE
134views Hardware» more  ICCD 2006»
14 years 1 months ago
Automated Design of Microfluidics-Based Biochips: Connecting Biochemistry to Electronics CAD
Microfluidics-based biochips offer exciting possibilities for highthroughput sequencing, parallel immunoassays, blood chemistry for clinical diagnostics, DNA sequencing, and envir...
Krishnendu Chakrabarty
VLSID
2009
IEEE
139views VLSI» more  VLSID 2009»
14 years 8 months ago
Improving Scalability and Per-Core Performance in Multi-Cores through Resource Sharing and Reconfiguration
Increasing the number of cores in a multi-core processor reduces per-core performance. On the other hand, providing more resources to each core limits the number of cores on a chi...
Tameesh Suri, Aneesh Aggarwal