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» On Reducing Circuit Malfunctions Caused by Soft Errors
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VLSID
2008
IEEE
117views VLSI» more  VLSID 2008»
14 years 7 months ago
Single Event Upset: An Embedded Tutorial
Abstract-- With the continuous downscaling of CMOS technologies, the reliability has become a major bottleneck in the evolution of the next generation systems. Technology trends su...
Fan Wang, Vishwani D. Agrawal
ASAP
2008
IEEE
142views Hardware» more  ASAP 2008»
14 years 1 months ago
Managing multi-core soft-error reliability through utility-driven cross domain optimization
As semiconductor processing technology continues to scale down, managing reliability becomes an increasingly difficult challenge in high-performance microprocessor design. Transie...
Wangyuan Zhang, Tao Li
DAC
2006
ACM
14 years 8 months ago
MARS-C: modeling and reduction of soft errors in combinational circuits
Due to the shrinking of feature size and reduction in supply voltages, nanoscale circuits have become more susceptible to radiation induced transient faults. In this paper, we pre...
Natasa Miskov-Zivanov, Diana Marculescu
VLSISP
2008
139views more  VLSISP 2008»
13 years 7 months ago
Fault Tolerance Analysis of Communication System Interleavers: the 802.11a Case Study
The study of Multiple Soft errors on memory modules caused by radiation effects represents an interesting field of current research. The fault tolerance of these devices in radiati...
Pilar Reyes, Pedro Reviriego, Juan Antonio Maestro...
ICCD
2006
IEEE
138views Hardware» more  ICCD 2006»
14 years 4 months ago
Delay and Area Efficient First-level Cache Soft Error Detection and Correction
—Soft error rates are an increasing problem in modern VLSI circuits. Commonly used error correcting codes reduce soft error rates in large memories and second level caches but ar...
Karl Mohr, Lawrence Clark