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» On Reducing Circuit Malfunctions Caused by Soft Errors
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VLSID
2003
IEEE
104views VLSI» more  VLSID 2003»
14 years 7 months ago
Analyzing Soft Errors in Leakage Optimized SRAM Design
Reducing leakage power and improving the reliability of data stored in the memory cells are both becoming challenging as technology scales down. While the smaller threshold voltag...
Vijay Degalahal, Narayanan Vijaykrishnan, Mary Jan...
IOLTS
2007
IEEE
155views Hardware» more  IOLTS 2007»
14 years 1 months ago
On Derating Soft Error Probability Based on Strength Filtering
— Soft errors caused by ionizing radiation have emerged as a major concern for current generation of CMOS technologies and the trend is expected to get worse. A significant frac...
Alodeep Sanyal, Sandip Kundu
ICCAD
2007
IEEE
116views Hardware» more  ICCAD 2007»
14 years 4 months ago
Device and architecture concurrent optimization for FPGA transient soft error rate
Late CMOS scaling reduces device reliability, and existing work has studied the permanent SER (soft error rate) for configuration memory in FPGA extensively. In this paper, we sh...
Yan Lin, Lei He
DATE
2006
IEEE
151views Hardware» more  DATE 2006»
14 years 1 months ago
Designing MRF based error correcting circuits for memory elements
As devices are scaled to the nanoscale regime, it is clear that future nanodevices will be plagued by higher soft error rates and reduced noise margins. Traditional implementation...
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, Will...
ICCD
2005
IEEE
92views Hardware» more  ICCD 2005»
14 years 4 months ago
Mitigating Soft Errors in Highly Associative Cache with CAM-based Tag
Content Addressable Memories (CAM) are widely used for the tag portions in highly associative caches. Since data are not explicitly read out of tag array in CAM search, the detect...
Luong Dinh Hung, Masahiro Goshima, Shuichi Sakai