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TVLSI
2008
133views more  TVLSI 2008»
13 years 7 months ago
Test Data Compression Using Selective Encoding of Scan Slices
We present a selective encoding method that reduces test data volume and test application time for scan testing of Intellectual Property (IP) cores. This method encodes the slices ...
Zhanglei Wang, Krishnendu Chakrabarty
ITC
2002
IEEE
114views Hardware» more  ITC 2002»
14 years 13 days ago
Scan Power Reduction Through Test Data Transition Frequency Analysis
Significant reductions in test application times can be achieved through parallelizing core tests; however, simultaneous test of various cores may result in exceeding power thres...
Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailog...
ICCD
2006
IEEE
116views Hardware» more  ICCD 2006»
14 years 4 months ago
RTL Scan Design for Skewed-Load At-speed Test under Power Constraints
This paper discusses an automated method to build scan chains at the register-transfer level (RTL) for powerconstrained at-speed testing. By analyzing a circuit at the RTL, where ...
Ho Fai Ko, Nicola Nicolici
VTS
2007
IEEE
143views Hardware» more  VTS 2007»
14 years 1 months ago
RTL Test Point Insertion to Reduce Delay Test Volume
In this paper, a novel test point insertion methodology is presented for RTL designs that aims to reduce the data volume of scan-based transition delay tests. Test points are iden...
Kedarnath J. Balakrishnan, Lei Fang
ICCAD
2004
IEEE
101views Hardware» more  ICCAD 2004»
14 years 4 months ago
Frugal linear network-based test decompression for drastic test cost reductions
— In this paper we investigate an effective approach to construct a linear decompression network in the multiple scan chain architecture. A minimal pin architecture, complemented...
Wenjing Rao, Alex Orailoglu, G. Su