2452 search results - page 298 / 491 » On Reduction of Lagrange Systems |
134
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ASPDAC
2005
ACM
15 years 6 months ago
2005
ACM
- The use of synthesizable reconfigurable cores in system on chip (SoC) designs is increasingly becoming a trend. Such domain-special cores are being used for their flexibility, po...
ASPDAC
2005
ACM
15 years 6 months ago
2005
ACM
– We propose a System-on-Chip (SoC) architecture for reconfigurable applications based on the AMBA HighSpeed Bus (AHB). The architecture features multiple low-area flyby DMA bloc...
137
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ASAP
2006
IEEE
15 years 6 months ago
2006
IEEE
This paper proposes a novel parallel approach for pipelining of nested multiplexer loops to design high speed decision feedback equalizers (DFEs) based on look-ahead techniques. I...
132
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DATE
2005
IEEE
15 years 6 months ago
2005
IEEE
In this paper, we provide a methodology to perform both bus partitioning and bus frequency assignment to each of the bus segment simultaneously while optimizing both power consump...
154
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DSN
2008
IEEE
15 years 6 months ago
2008
IEEE
The combination of continued technology scaling and increased on-chip transistor densities has made vulnerability to radiation induced soft errors a significant design concern. In...