13 search results - page 1 / 3 » On Removing Multiple Redundancies in Combinational Circuits |
DATE
1998
IEEE
14 years 3 months ago
1998
IEEE
1 Redundancy removal is an important step in combinational logic optimization. After a redundant wire is removed, other originally redundant wires may become irredundant, and some ...
ICCD
1996
IEEE
14 years 3 months ago
1996
IEEE
For circuits where there may be latches with no reset line, we show how to replace some of them with combinational logic. All previous work in sequential optimization by latch rem...
TC
2010
13 years 9 months ago
2010
—Due to the widespread use and inherent complexity of floating-point addition, much effort has been devoted to its speedup via algorithmic and circuit techniques. We propose a ne...
TCAD
2008
13 years 10 months ago
2008
Abstract--Simplifying a combinational circuit while preserving its range has a variety of applications, such as combinational equivalence checking and random simulation. Previous a...
DATE
2000
IEEE
14 years 3 months ago
2000
IEEE
This paper presents a method for redundancy identification (RID) using multi-node logic implications. The algorithm discovers a large number of direct and indirect implications b...