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» On Some Systems Controlled by the Structure of Their Memory
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ISCA
2010
IEEE
205views Hardware» more  ISCA 2010»
14 years 1 months ago
The virtual write queue: coordinating DRAM and last-level cache policies
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...
DAC
2007
ACM
14 years 9 months ago
A System For Coarse Grained Memory Protection In Tiny Embedded Processors
Many embedded systems contain resource constrained microcontrollers where applications, operating system components and device drivers reside within a single address space with no...
Ram Kumar, Akhilesh Singhania, Andrew Castner, Edd...
ICS
2003
Tsinghua U.
14 years 1 months ago
miNI: reducing network interface memory requirements with dynamic handle lookup
Recent work in low-latency, high-bandwidth communication systems has resulted in building user–level Network InControllers (NICs) and communication abstractions that support dir...
Reza Azimi, Angelos Bilas
GECCO
2007
Springer
217views Optimization» more  GECCO 2007»
13 years 10 months ago
A quantitative analysis of memory requirement and generalization performance for robotic tasks
In autonomous agent systems, memory is an important element to handle agent behaviors appropriately. We present the analysis of memory requirements for robotic tasks including wal...
DaeEun Kim
ICCAD
1994
IEEE
76views Hardware» more  ICCAD 1994»
14 years 23 days ago
An efficient procedure for the synthesis of fast self-testable controller structures
The BIST implementation of a conventionally synthesized controller in most cases requires the integration of an additional register only for test purposes. This leads to some seri...
Sybille Hellebrand, Hans-Joachim Wunderlich