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ASPDAC
2007
ACM
92views Hardware» more  ASPDAC 2007»
13 years 11 months ago
New Block-Based Statistical Timing Analysis Approaches Without Moment Matching
With aggressive scaling down of feature sizes in VLSI fabrication, process variation has become a critical issue in designs. We show that two necessary conditions for the "Ma...
Ruiming Chen, Hai Zhou
ISCAS
2005
IEEE
131views Hardware» more  ISCAS 2005»
14 years 17 days ago
Timing yield estimation using statistical static timing analysis
—As process variations become a significant problem in deep sub-micron technology, a shift from deterministic static timing analysis to statistical static timing analysis for hig...
Min Pan, Chris C. N. Chu, Hai Zhou
DAC
2007
ACM
14 years 8 months ago
Confidence Scalable Post-Silicon Statistical Delay Prediction under Process Variations
Due to increased variability trends in nanoscale integrated circuits, statistical circuit analysis has become essential. We present a novel method for post-silicon analysis that g...
Qunzeng Liu, Sachin S. Sapatnekar
DAC
2004
ACM
13 years 10 months ago
Statistical gate delay model considering multiple input switching
There is an increased dominance of intra-die process variations, creating a need for an accurate and fast statistical timing analysis. Most of the recent proposed approaches assum...
Aseem Agarwal, Florentin Dartu, David Blaauw
DAC
2005
ACM
13 years 9 months ago
Parameterized block-based statistical timing analysis with non-gaussian parameters, nonlinear delay functions
Variability of process parameters makes prediction of digital circuit timing characteristics an important and challenging problem in modern chip design. Recently, statistical stat...
Hongliang Chang, Vladimir Zolotov, Sambasivan Nara...