82 search results - page 8 / 17 » On Structural vs. Functional Testing for Delay Faults |
ETS
2007
IEEE
14 years 1 months ago
2007
IEEE
The paper proposes a new concept of diagnosing faulty links in Network-on-a-Chip (NoC) designs. The method is based on functional fault models and it implements packet address dri...
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
Functional verification of microprocessors is one of the most complex and expensive tasks in the current system-on-chip design process. A significant bottleneck in the validatio...
ET
2006
13 years 7 months ago
2006
We present an efficient built-in self-test (BIST) architecture for testing and diagnosing stuck-at faults, delay faults, and bridging faults in FPGA interconnect resources. The BIS...
GLVLSI
2010
IEEE
14 years 22 days ago
2010
IEEE
NBTI is one of the most important silicon reliability problems facing processor designers today. The impact of NBTI can be mitigated at both the circuit and microarchitecture leve...
GLVLSI
2007
IEEE
14 years 1 months ago
2007
IEEE
The path-delay fault simulation of functional tests on complex circuits such as current processor-based systems is a daunting task. The amount of computing power and memory needed...