1529 search results - page 101 / 306 » On Timing Analysis of Combinational Circuits |
122
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ICCD
2005
IEEE
16 years 1 months ago
2005
IEEE
Consideration of pairs of transition in probabilistic simulation allows power estimation for digital circuits in which inertial delays can filter glitches [5]. However, the merit ...
125
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EUROGP
2000
Springer
15 years 8 months ago
2000
Springer
1 The function level evolvable hardware approach to synthesize the combinational multiple-valued and binary logic functions is proposed in rst time. The new representation of logic...
139
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DAC
2012
ACM
13 years 7 months ago
2012
ACM
Near-threshold operation has emerged as a competitive approach for energy-efficient architecture design. In particular, a combination of near-threshold circuit techniques and par...
159
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DATE
2009
IEEE
15 years 11 months ago
2009
IEEE
—Verification is a major issue in circuit and system design. Formal methods like bounded model checking (BMC) can guarantee a high quality of the verification. There are severa...
143
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FTEDA
2007
15 years 4 months ago
2007
The number of gates on a chip is quickly growing toward and beyond the one billion mark. Keeping all the gates running at the beat of a single or a few rationally related clocks i...