1529 search results - page 107 / 306 » On Timing Analysis of Combinational Circuits |
ICCAD
2003
IEEE
14 years 5 months ago
2003
IEEE
Under modern VLSI technology, process variations greatly affect circuit performance, especially clock skew which is very timing sensitive. Unwanted skew due to process variation f...
ISQED
2008
IEEE
14 years 2 months ago
2008
IEEE
— The dominant substrate noise coupling mechanism is determined for multiple switching gates based on a physically intuitive model. The model exhibits reasonable accuracy as comp...
FPGA
2007
ACM
14 years 2 months ago
2007
ACM
Chip design in the nanometer regime is becoming increasingly difficult due to process variations. ASIC designers have adopted statistical optimization techniques to mitigate the e...
DAC
2007
ACM
14 years 8 days ago
2007
ACM
With the continuous increase of circuit density, interconnect length, and aspect ratio, the influence of capacitive and inductive coupling on timing characteristics of integrated ...
EURODAC
1995
IEEE
13 years 12 months ago
1995
IEEE
Because it costs to solve ElectroMagnetic Compatibility (EMC) problems late in the development process, new methods have to predict radiated electromagnetic emissions at the desig...