1529 search results - page 110 / 306 » On Timing Analysis of Combinational Circuits |
DEDS
2010
13 years 8 months ago
2010
Abstract-- We address the problem of batching messages generated at nodes of a sensor network for the purpose of reducing communication energy at the expense of added latency. We f...
ASPDAC
2007
ACM
14 years 10 days ago
2007
ACM
Many current integrated circuits designs, such as those released for the ISPD2005[14] placement contest, are extremely large and can contain a great deal of white space. These new...
ICCD
2007
IEEE
14 years 5 months ago
2007
IEEE
This paper proposes an efficient analysis flow and an algorithm to identify the worst case noise for power networks with multiple clock domains. First, we apply the Laplace transf...
ISLPED
2003
ACM
14 years 1 months ago
2003
ACM
Enabled by the continuous advancement in fabrication technology, present day synchronous microprocessors include more than 100 million transistors and have clock speeds well in ex...
DAC
2006
ACM
14 years 9 months ago
2006
ACM
Three-dimensional (3-D) integrated circuits have emerged as promising candidates to overcome the interconnect bottlenecks of nanometer scale designs. While they offer several othe...