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» On Variations of Power Iteration
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DAC
2006
ACM
14 years 9 months ago
A novel variation-aware low-power keeper architecture for wide fan-in dynamic gates
Substantial increase in leakage current and threshold voltage fluctuations are making design of robust wide fan-in dynamic gates a challenging task. Traditionally, a PMOS keeper t...
Hamed F. Dadgour, Rajiv V. Joshi, Kaustav Banerjee
ICCAD
2005
IEEE
114views Hardware» more  ICCAD 2005»
14 years 4 months ago
Double-gate SOI devices for low-power and high-performance applications
: Double-Gate (DG) transistors have emerged as promising devices for nano-scale circuits due to their better scalability compared to bulk CMOS. Among the various types of DG device...
Kaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhop...
MICRO
2009
IEEE
178views Hardware» more  MICRO 2009»
14 years 2 months ago
Improving cache lifetime reliability at ultra-low voltages
Voltage scaling is one of the most effective mechanisms to reduce microprocessor power consumption. However, the increased severity of manufacturing-induced parameter variations a...
Zeshan Chishti, Alaa R. Alameldeen, Chris Wilkerso...
RTAS
2008
IEEE
14 years 2 months ago
A Hybrid DVS Scheme for Interactive 3D Games
Interactive 3D games are now widely available on a variety of mobile devices for which battery-life is a major concern. Many of these devices support voltage/frequencyscalable pro...
Yan Gu, Samarjit Chakraborty
DATE
2006
IEEE
104views Hardware» more  DATE 2006»
14 years 2 months ago
Integrated placement and skew optimization for rotary clocking
—The clock distribution network is a key component of any synchronous VLSI design. High power dissipation and pressure volume temperature-induced variations in clock skew have st...
Ganesh Venkataraman, Jiang Hu, Frank Liu, Cliff C....