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» On Variations of Power Iteration
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FCCM
2008
IEEE
118views VLSI» more  FCCM 2008»
14 years 4 months ago
A New Powerful Scalable Generic Multi-Standard LDPC Decoder Architecture
We propose a new powerful scalable generic parallel and modular architecture well suited to LDPC code decoding. This architecture template has been instantiated in the case of the...
François Charot, Christophe Wolinski, Nicol...
VLDB
1987
ACM
93views Database» more  VLDB 1987»
14 years 1 months ago
FAD, a Powerful and Simple Database Language
FAD is a powerful and simple language designed for a highly parallel database machine. The basic concepts of the language are its data structures (which we call objects) and its p...
François Bancilhon, Ted Briggs, Setrag Khos...
DAC
1999
ACM
14 years 11 months ago
A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design
We propose a method for power optimization that considers glitch reduction by gate sizing based on the statistical estimation of glitch transitions. Our method reduces not only th...
Masanori Hashimoto, Hidetoshi Onodera, Keikichi Ta...
INFOCOM
2002
IEEE
14 years 3 months ago
On Distinguishing between Internet Power Law Topology Generators
— Recent work has shown that the node degree in the WWW induced graph and the AS-level Internet topology exhibit power laws. Since then several algorithms have been proposed to g...
Tian Bu, Donald F. Towsley
DATE
2005
IEEE
109views Hardware» more  DATE 2005»
14 years 4 months ago
Design Method for Constant Power Consumption of Differential Logic Circuits
Side channel attacks are a major security concern for smart cards and other embedded devices. They analyze the variations on the power consumption to find the secret key of the en...
Kris Tiri, Ingrid Verbauwhede