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» On a quasi-ordering on Boolean functions
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STOC
2002
ACM
115views Algorithms» more  STOC 2002»
14 years 8 months ago
Reimer's inequality and tardos' conjecture
Let f : {0, 1}n {0, 1} be a boolean function. For 0 let D (f) be the minimum depth of a decision tree for f that makes an error for fraction of the inputs x {0, 1}n . We also ma...
Clifford D. Smyth
ICCD
2005
IEEE
116views Hardware» more  ICCD 2005»
14 years 4 months ago
Enhanced Dual-Transition Probabilistic Power Estimation with Selective Supergate Analysis
Consideration of pairs of transition in probabilistic simulation allows power estimation for digital circuits in which inertial delays can filter glitches [5]. However, the merit ...
Fei Hu, Vishwani D. Agrawal
ICCD
2001
IEEE
176views Hardware» more  ICCD 2001»
14 years 4 months ago
BDD Variable Ordering by Scatter Search
Reduced Ordered Binary Decision Diagrams (BDDs) are a data structure for representation and manipulation of Boolean functions which are frequently used in VLSI Design Automation. ...
William N. N. Hung, Xiaoyu Song
DATE
2009
IEEE
113views Hardware» more  DATE 2009»
14 years 2 months ago
Exploiting structure in an AIG based QBF solver
—In this paper we present a procedure for solving quantified boolean formulas (QBF), which uses And-Inverter Graphs (AIGs) as the core data-structure. We make extensive use of s...
Florian Pigorsch, Christoph Scholl
DSD
2007
IEEE
87views Hardware» more  DSD 2007»
14 years 2 months ago
On the Construction of Small Fully Testable Circuits with Low Depth
During synthesis of circuits for Boolean functions area, delay and testability are optimization goals that often contradict each other. Multi-level circuits are often quite small ...
Görschwin Fey, Anna Bernasconi, Valentina Cir...