100 search results - page 5 / 20 » On hierarchical statistical static timing analysis |
ICCAD
2005
IEEE
14 years 5 months ago
2005
IEEE
— As technology scales into the sub-90nm domain, manufacturing variations become an increasingly significant portion of circuit delay. As a result, delays must be modeled as sta...
DATE
2007
IEEE
14 years 2 months ago
2007
IEEE
A vast literature has been published on Statistical Static Timing Analysis (SSTA), its motivations, its different implementations and their runtime/accuracy trade-offs. However, v...
ICCAD
2005
IEEE
14 years 5 months ago
2005
IEEE
— Variability in the chip design process has been relatively increasing with technology scaling to smaller dimensions. Using worst case analysis for circuit optimization severely...
ICCAD
2003
IEEE
14 years 5 months ago
2003
IEEE
Static timing analysis is a critical step in design of any digital integrated circuit. Technology and design trends have led to significant increase in environmental and process v...
ICCAD
2009
IEEE
13 years 6 months ago
2009
IEEE
Process and environmental variations continue to present significant challenges to designers of high-performance integrated circuits. In the past few years, while much research has...