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» On modeling top-down VLSI design
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DSD
2009
IEEE
111views Hardware» more  DSD 2009»
14 years 2 months ago
Robustness Check for Multiple Faults Using Formal Techniques
Feature sizes in VLSI circuits are steadily shrinking. This results in increasing susceptibility to soft errors, e.g. due to environmental radiation. Precautions against soft error...
Stefan Frehse, Görschwin Fey, André S&...
FCCM
2002
IEEE
143views VLSI» more  FCCM 2002»
14 years 15 days ago
An FPGA Implementation of Triangle Mesh Decompression
This paper presents an FPGA-based design and implementation of a three dimensional (3D) triangle mesh decompressor. Triangle mesh is the dominant representation of 3D geometric mo...
Tulika Mitra, Tzi-cker Chiueh
FCCM
2000
IEEE
114views VLSI» more  FCCM 2000»
13 years 12 months ago
Tunable Fault Tolerance for Runtime Reconfigurable Architectures
Fault tolerance is becoming an increasingly important issue, especially in mission-critical applications where data integrity is a paramount concern. Performance, however, remains...
Steven K. Sinha, Peter Kamarchik, Seth Copen Golds...
GLVLSI
2000
IEEE
110views VLSI» more  GLVLSI 2000»
13 years 12 months ago
A sensitivity based placer for standard cells
We present a new timing driven method for global placement. Our method is based on the observation that similar net length reductions in the different nets that make up a path may...
Bill Halpin, C. Y. Roger Chen, Naresh Sehgal
VLSID
1999
IEEE
111views VLSI» more  VLSID 1999»
13 years 11 months ago
A New Approach for CMOS Op-Amp Synthesis
A new approach for CMOS op-amp circuit synthesis has proposed here. The approach is based on the observation that the rst order behavior of a MOS transistor in the saturation regi...
Pradip Mandal, V. Visvanathan