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» On modeling top-down VLSI design
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SBCCI
2003
ACM
135views VLSI» more  SBCCI 2003»
14 years 24 days ago
Modeling a Reconfigurable System for Computing the FFT in Place via Rewriting-Logic
The growing adoption of reconfigurable architectures opens new implementation alternatives and creates new design challenges. In the case of dynamically reconfigurable architectur...
Mauricio Ayala-Rincón, Rodrigo B. Nogueira,...
DAC
2005
ACM
14 years 8 months ago
A lattice-based framework for the classification and design of asynchronous pipelines
This paper presents a unifying framework for the modeling of asynchronous pipeline circuits. A pipeline protocol is captured in a graph-based model which defines the partial order...
Peggy B. McGee, Steven M. Nowick
ICCAD
2008
IEEE
246views Hardware» more  ICCAD 2008»
14 years 4 months ago
Integrated circuit design with NEM relays
—To overcome the energy-efficiency limitations imposed by finite sub-threshold slope in CMOS transistors, this paper explores the design of integrated circuits based on nanoelect...
Fred Chen, Hei Kam, Dejan Markovic, Tsu-Jae King L...
SBCCI
2006
ACM
126views VLSI» more  SBCCI 2006»
14 years 1 months ago
Power constrained design optimization of analog circuits based on physical gm/ID characteristics
This paper presents a transistor optimization methodology for low-power analog integrated CMOS circuits, relying on the physics-based gm/ID characteristics as a design optimizatio...
Alessandro Girardi, Sergio Bampi
VLSID
2001
IEEE
129views VLSI» more  VLSID 2001»
14 years 8 months ago
Design Of Provably Correct Storage Arrays
In this paper we describe a hardware design method for memory and register arrays that allows the application of formal equivalence checking for comparing a high-level register tr...
Rajiv V. Joshi, Wei Hwang, Andreas Kuehlmann