305 search results - page 37 / 61 » On modeling top-down VLSI design |
GLVLSI
2002
IEEE
14 years 13 days ago
2002
IEEE
Many computation-intensive or recursive applications commonly found in digital signal processing and image processing applications can be represented by data-flow graphs (DFGs). ...
GLVLSI
2009
IEEE
13 years 5 months ago
2009
IEEE
To assist in dynamic assertion-based verification, we present a method to automatically build a test vector generator from a temporal property. Based on the duality between monito...
VLSID
2003
IEEE
14 years 7 months ago
2003
IEEE
There is an increasing need for obtaining a reasonably accurate estimate of energy dissipation in SoC designs. Array structures have a significant contribution to the total system...
VLSID
2005
IEEE
2005
IEEE
Formal Methods for Analyzing the Completeness of an Assertion Suite against a High-Level Fault Model
14 years 1 months ago
One of the emerging challenges in formal property verification (FPV) technology is the problem of deciding whether sufficient properties have been written to cover the design in...
GLVLSI
2007
IEEE
13 years 11 months ago
2007
IEEE
Reliability modeling and evaluation is expected to be one of the major issues in emerging nano-devices and beyond 22nm CMOS. Such devices would have inherent propensity for gate f...